Devices known as timers, i.e. timing units, are routinely used in the prior art to support a processor, such as a CPU (Central Processing Unit) for example, for time-based and position-based processes. Such timing units can be designed as individual components or as peripheral devices to the processor, where, on the basis of one or more clocks, they time the provision of functions of varying importance for receiving and generating signals.
According to the current prior art, various architectures for implementing timing units are used in processors, such as microcontrollers, for example. There can basically be two different architecture variants here.
A first variant is a pure hardware implementation of a timing module, which must be operated and configured from a processor such as a CPU, for example. The timing module itself is then used for signal acquisition and characterization and is also capable of generating output signals of limited complexity. Such timing modules, however, are generally characterized by a high “interrupt load”, because the hardware of the respective processor must be supplied with new parameters or parameters must be retrieved from the relevant hardware.
An example of an architecture of this type is the General Purpose Timer Array (GPTA) from Infinion and the Advanced Timer Unit (ATU) from Renesas™.
In contrast, a second architecture variant permits a certain degree of internal programmability of the respective timing unit. In this case, the timing unit or timing module can itself execute a program together with data, and operate input and output units accordingly. An architecture implemented in this way reduces the aforementioned interrupt load on the processor, i.e. on the central processing unit, in that many internal events of the timing unit are handled by an internal processor of the timing unit. Thus this type of architecture implements a form of small microcontroller for processing time-dependent data in the respective timing units. This implemented small microcontroller is then combined with input and output units that have a relatively low configuration. It must be mentioned here, however, that such systems are limited by interrupt latency and sequential interrupt handling, i.e. the microcontroller handles a plurality of different functions, each of which make a request to this microcontroller by interrupt, and these interrupts are processed sequentially (including the relevant delays).
The less complex variant of the aforementioned timing units is implemented, for example, by Infinion in the GPTA (General Purpose Timer Array) or by Renesas in the corresponding Advanced Timer Unit (ATU). The second, slightly more complex variant of the aforementioned timing units is implemented, for example, by Freescale™ in their Timer Processing Unit (TPU) or by Texas Instruments (TI) in their High-End Timer (HET).
In DE 10 2007 044 803, timing modules are connected together via a time routing unit TRU. These timing modules can be input and output modules in this case.
The mentioned limitations of the timing units provided in the prior art and of their respective implementation mean that it would be desirable to provide a facility not only to reduce an interrupt load on a relevant processor, which for data processing can be considered to be a central processing unit, but also to be able to handle as many processes as possible in parallel and in real time, i.e. promptly, without being restricted by an incoming number of interrupts or a number of interrupt sources.